Forget one chip to rule them all: With TPU 8, Google has an AI arms race to win

Both TPU 8 accelerators will be generally available later this year in Google Cloud Platform as instances, or as part of the cloud provider's full-stack AI Hypercomputer platform, which bundles up all ...
MIT Technology Review

Analog computing from waste heat

Harnessing heat generated by a device itself, microscopic silicon structures could lead to more energy-efficient thermal ...
Semiconductor Engineering

Research Bits: Apr. 21

Compute-in-memory: State space models; ultra-thin AlScN memory; brain-inspired edge AI.
Semiconductor Engineering

Heterogeneous NPU Data Movement: What The Execution Flow Shows

Heterogeneous NPU designs bring together multiple specialized compute engines to support the range of operators required by ...
Communications of the ACM

The Origins of GPU Computing

Government-funded academic research on parallel computing, stream processing, real-time shading languages, and programmable ...
Tech Xplore

A hardware-software co-design can efficiently run AI on edge devices

A new hardware-software co-design increases AI energy efficiency and reduces latency, enabling real-time processing of ...
IEEE

Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors

Abstract: Structured sparsity has been proposed as an efficient way to prune the complexity of Machine Learning (ML) applications and to simplify the handling of sparse data in hardware. Accelerating ...
EDN

RISC-V IP expands AI capabilities at the edge

SiFive’s Intelligence Gen 2 RISC-V IP portfolio combines scalar, vector, and matrix compute to accelerate AI workloads. The Gen 2 lineup includes the new X160 and X180, alongside the upgraded X280, ...
eeworldonline

RISC-V processors add matrix processing for AI workloads

SiFive launched its 2nd Generation Intelligence™ family, featuring five new RISC-V-based products designed to accelerate AI workloads across applications. The lineup includes two new products — the ...